MiniMax 8085

MiniMax 8085


The MiniMax8085 project has been brewing for almost three years. Sometime in the spring of 2014 my kids and I visited local the surplus store, where my kids found some Intel 8000 series parts in the kids-fill-your-bucket area. Among these ICs were there: an 8085 CPU, an 8155 RAM with I/O ports and timer, a couple of 8255 PPIs, an 8282 latch, and some 27C128 UV EPROMs. It looked like a good start for an 8085 based computer that can be used to teach my kids some computer design and programming basics.
I wanted the project to be simple to build, with a minimal number of components, but yet to be a fully functional single board computer (e.g. to include the memory and an input/output device, for example a UART) with an extension bus. I checked the Internet for existing homebrew 8085 computers and found Roman Fülek’s NCB85 and NCB85v2 projects, and Glitch Works 8085 projects. While I liked these projects, they didn’t quite meet my project design goals:



  • NCB85 was the closest, but it doesn’t have an extension bus
  • NCB85v2 is a little bit too complicated for my needs
  • Glitch Works 8085 project didn’t have an on-board UART

The resulting design includes 8085 CPU, 8251 USART, 32 KiB SRAM, 32 KiB or 16 KiB ROM. It uses a GAL16V8/ATF16V8 simple programmable logic device (SPLD) instead of discrete logic ICs for the address decode and the frequency divider for USART. It reduces the number of components, allows for tweaking the configuration by re-programming the SPLD, and provides an introduction to the programmable logic devices. – web link to were i got the project files



  • 80C85A or 8085A CPU, 3.072 MHz or 4.9152 MHz CPU clock frequency
  • 82C51A or 8251A USART for console connection
  • 32 KiB of battery backed SRAM
  • Up to 32 KiB of ROM. EEPROM, UV EPROM or Flash ROM memory is supported
  • 40-pin extension bus connector, including most of 8085 signals and demultiplexed data and address buses

Design Description


The MiniMax8085 is based on the Intel 8085A CPU. The 74*573 octal latch is used to demultiplex the lower 8-bit of address and data bus.
The board uses the Intel 8251A USART for serial input / output, for example for connecting a console.

The MAX232A RS-232 driver/receiver is used to convert TTL logic levels to RS-232 voltage.
The 62256 32 KiB SRAM (U4) is used for the system RAM. The RAM is battery backed using the DS1210 NVRAM controller (U8).
The board supports a variety of ROM options. The 28C256 EEPROM; UV EPROMs, such as 27C256 (32 KiB), 27C128 (16 KiB), and 27C64 (8 KiB); or The 29C256 Flash ROM ICs. Normally the ROM is mapped to the CPU memory beginning from the address 0x0000, while the RAM is mapped beginning from the address 0x8000. The ROM and RAM addresses can be swapped by pulling /SWAP_MEM signal low. This can be used, for example, to implement a CP/M extension card.
The GAL16V8 simple programmable logic device  implements all the required “glue” logic functions:


  • Address decode and chip select for the USART. The default USART I/O address is 0x08.
  • Clock divider that divides the CPU clock to obtain USART transmit and receive clock. The divisor value depends on the CPU speed. Fuse maps with divide by 10 and 20, divide by 13 and 26, and divide by 16 and 32 ratios are provided to support common 8085A CPU clocks: 3.072 MHz, 4 MHz, 4.9152 MHz, 6.144 MHz, and 8 MHz.
  • Address decode and chip select for the ROM and SRAM. The address decode logic include additional /SWAP_MEM input, which by default is configured to swap address mapping of ROM and RAM.

Please refer to the Simple Programmable Logic Device section below for more details regarding the SPLD configuration and programming.
The MiniMax8085 includes a 40-pin extension connector (P4), that features the 8085A address and data buses, and control signals. Please refer to the Jumpers and Connectors section below for the connector pinout and signals description.




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